1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly to an energy recovery circuit for use in a driving apparatus of the plasma display panel and a driving method thereof.
2. Background of the Related Art
A plasma display panel (hereinafter, referred to as a ‘PDP’) is adapted to display an image including characters or graphics by light-emitting phosphors with ultraviolet (147 nm) generated during the discharge of an inert mixed gas such as He+Xe, Ne+Xe or He+Ne+Xe, or the like. This PDP can be easily made thin and large, and it can provide greatly increased image quality with the recent development of the relevant technology. Particularly, a three-electrode AC surface discharge type PDP has advantages of lower driving voltage and longer product lifespan as a wall charge is accumulated on a surface in discharging and electrodes are protected from sputtering caused by discharging.
FIG. 1 is a perspective view showing the configuration of a discharge cell of a conventional plasma display panel. Referring now to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode Y and a sustain electrode Z which are formed on an upper substrate 10, and an address electrode X formed on a lower substrate 18. Each of the scan electrode Y and the sustain electrode Z include transparent electrodes 12Y and 12Z, and metal bus electrodes 13Y and 13Z which have a line width smaller than that of the transparent electrodes 12Y and 12Z and are respectively disposed at one side edges of the transparent electrodes.
The transparent electrodes 12Y and 12Z, which are generally made of ITO (indium tin oxide), are formed on the upper substrate 10. The metal bus electrodes 13Y and 13Z are generally formed on the transparent electrodes 12Y and 12Z made of metal such as chromium (Cr), and serves to reduce a voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance.
On the upper substrate 10 in which the scan electrode Y and the sustain electrode Z are placed parallel to each other is laminated an upper dielectric layer 14 and a protective layer 16. The upper dielectric layer 14 is accumulated with a wall charge generated during plasma discharging. The protective layer 16 is adapted to prevent damages of the upper dielectric layer 14 due to sputtering caused during plasma discharging, and improve efficiency of secondary electron emission. As the protective layer 16, magnesium oxide (MgO) is generally used.
A lower dielectric layer 22 and a barrier rib 24 are formed on the lower substrate 18 in which the address electrode X is formed. A phosphor layer 26 is applied to the surfaces of both the lower dielectric layer 22 and the barrier rib 24.
The address electrode X is formed on the lower substrate 18 in the direction in which the scan electrode Y and the sustain electrode Z intersect with each other. The barrier rib 24 is in the form of stripe or lattice to prevent leakage of an ultraviolet and a visible light generated by discharging to an adjacent discharge cell. The phosphor layer 26 is excited with an ultraviolet generated during the plasma discharging to generate any one visible light of red, green and blue lights. An inert mixed gas is injected into the discharge spaces defined between the upper substrate 10 and the barrier ribs 24 and between the lower substrate 18 and the barrier ribs 24.
This three-electrode AC surface discharge type PDP is divided into a plurality of sub-fields and is driven. In the period of each of the sub-fields, lights are emitted by the number proportionate to a weighted value of video data, thereby displaying gradations. The plurality of sub-fields are sub-divided into a reset period, an address period, a sustain period and a blanking period, and are driven.
Herein, the reset period is a period for forming an uniform wall charge on the discharge cell, the address period is a period for generating an selective address discharge according to a logical value the video data, and the sustain period is a period for maintaining discharge in the discharge cell from which the address discharge is generated.
As such, an address discharge and a sustain discharge of the AC surface discharge type PDP driven require high voltage of more than several hundreds of volts. Thus, in order to minimize the driving power necessary for the address discharge and the sustain discharge, an energy recovery circuit is used. The energy recovery circuit may recover the voltage between the scan electrode Y and the sustain electrode Z, and may be used as a driving voltage necessary for the subsequent discharge.
FIG. 2 is a circuit diagram showing an energy recovery circuit formed on the scan electrode Y for recovering a voltage of the sustain discharge. Practically, the energy recovery circuit is placed symmetrically to the sustain electrode Z with respect to a central panel capacitor (Cp).
Referring to FIG. 2, a conventional energy recovery circuit includes an inductor L which is connected between a panel capacitor Cp and a source capacitor Cs, a first switch S1 and a third switch S3 which are connected in parallel between the source capacitor Cs and the inductor L, diodes D5 and D6 which are disposed between the first and third switches S1, S3 and the inductor L, and a second switch S2 and the fourth switch S4 which are connected in parallel between the inductor L and the panel capacitor Cp.
The Panel capacitor Cp represents an equivalent circuit of capacitance which is formed between the scan electrode Y and the sustain electrode Z. The second switch S2 is connected to a reference voltage source Vs, and the fourth switch S4 is connected to a base voltage source GND. The source capacitor Cs recovers and charges the voltage which is charged to the panel capacitor Cp during sustain discharging, and provides again the charged voltage to the panel capacitor cp.
To this end, the source capacitor Cs has a capacitance capable of charging the voltage of Vs/2 that corresponds to a half of the reference voltage source Vs. The inductor L forms a resonant circuit together with the panel capacitor Cp. The first to fourth switches S1 to S4 control the flows of current. The fifth diode D5 and the sixth diode D6 both prevent the flow of electric current from reversing. Further, the internal diodes D1 to D4 each disposed within the first to fourth switches S1 to S4 also prevent the flow of electric current from reversing.
FIG. 3 is a timing and waveform diagram showing ON/OFF timings of the switches and output waveforms of the panel capacitors of FIG. 2.
The operation procedure will now be explained on the assumption that the panel capacitor Cp is charged with a voltage of 0 volt and the source capacitor Cs is charged with a voltage of Vs/2 before a period of T1.
In a period of T1, the first switch S1 is turned on, so that an electric current path is formed from the source capacitor Cs to the panel capacitor Cp through the first switch S1 and the inductor L. When the path of electric current is formed, the voltage of Vs/2 charged to the source capacitor Cs is supplied to the panel capacitor Cp. In this time, the inductor L and the panel capacitor Cp form a serial resonant circuit, so that the panel capacitor Cp is charged with the voltage of Vs that is twice the voltage of the source capacitor Cs.
In a period of T2, the second switch S2 is turned on. When the second switch S2 is turned on, the panel capacitor Cp is provided with voltage of the reference voltage source Vs. That is, when the second switch S2 is turned on, the voltage value of the reference voltage source Vs is supplied to the panel capacitor Cp, and hence it is prevented that the voltage value of the panel capacitor Cp become lower than that of the reference voltage source Vs, thereby generating a stable sustain discharge. At this time, because the voltage of the panel capacitor Cp rises up to Vs during a period of T1, the voltage value which is supplied from the outside during a period of T2 may be minimized (that is, it is possible to reduce a power consumption).
In a period of T3, the first switch S1 is turned off. In this time, the panel capacitor Cp maintains the voltage of the reference voltage source Vs. In a period of T4, the second switch S2 is turned off and the third switch S3 is turned on. When the third switch S3 is turned on, an electrical current path is formed from the panel capacitor Cp to the source capacitor Cs through the inductor L and the third switch S3, and the source capacitor Cs recovers the voltage which is charged to the panel capacitor. In this time, the source capacitor Cs is charged with a voltage of Vs/2.
In a period of T5, the third switch S3 is turned off and the fourth switch S4 is turned on. When the fourth switch S4 is turned on, an electric current path is formed between the panel capacitor Cp and the base voltage source GND, and the voltage of the panel capacitor Cp drops to 0 volts. In a period of T6, a state of T5 is remained for a given time period. Practically, an AC driving pulse which is supplied to the scan electrode Y and the sustain electrode Z may be obtained by periodically cycling the periods of T1 to T6.
However, the energy recovery circuit driven according to the aforementioned manner has a problem that the manufacturing cost is increased because the circuit uses the switching elements S1 to S4 having a high internal voltage. More specifically, a first node n1 is supplied with a voltage from the reference voltage source Vs, so that the second switch S2 and the fourth switch S4 must have a higher internal voltage than Vs.
On the other hand, in a normal operation of the energy recovery circuit, a second node n2 is supplied with a voltage of Vs. The source capacitor Cs is charged with a voltage of Vs/2. Therefore, in a normal operation of the energy recovery circuit, the third switch S3 requires only an internal voltage corresponding to a voltage of Vs/2 which is obtained by subtracting a voltage charged to the source capacitor Cs from a voltage applied to the second node n2. However at an initial operation of the energy recovery circuit, since the source capacitor Cs is not charged with voltage, that is, a potential of the source capacitor Cs is set to about 0 volt, an internal voltage of the third switch S3 must be set to a voltage higher than Vs. And the source capacitor Cs is charged with a voltage of Vs/2.
Practically, in order for the source capacitor Cs to be charged with a voltage of Vs/2, the processes of T1 to T6 as shown in FIG. 3 should be repeatedly performed several times. Also, during this processes a value of the voltage applied to across the third switch S3 gradually lowers from Vs to Vs/2, thus an internal voltage of the third switch S3 is set to about Vs.
Furthermore, the first switch S1 is used only when a voltage of the source capacitor Cs is supplied to the inductor L. In this time, a difference in voltage across the first switch S1 is set to a voltage of Vs/2. Therefore, in a normal operation of the energy recovery circuit, the first switch S1 requires only an internal voltage of Vs/2. However, when a base potential is applied to the second node n2, the second node n2 is connected to the base voltage source GND via the inductor L and the fourth switch S4. In this time, a voltage of the second node n2 drops to a potential smaller than that of the base voltage source GND due to peaking phenomenon. Therefore, in the prior art, an internal voltage of the first switch S1 is set to approximately Vs, so that the first switch S1 is prevented from being damaged. That is, all of the first to fourth switches S1 to S4 used in the conventional energy recovery circuit are designed to have a higher internal voltage than Vs, which contributes to an increase in manufacturing cost.